(1) FIELD OF THE INVENTION
This invention relates to semiconductor integrated circuits and more specifically to a method of fabrication used for semiconductor integrated circuit devices, whereby the reliability and interlevel adhesion of multilayer structures of FSG (F-doped SiO2) dielectric layers and metal conducting layers are improved.
(2) DESCRIPTION OF RELATED ART
In the fabrication of semiconductor integrated circuits multilayer structures of dielectric layers and patterned conducting layers are used to form the interconnections between discrete devices formed in or on a semiconductor substrate. Depending upon the levels of integration required, one or more conducting layers with the appropriate interconnection patterns are formed alternately with interlevel dielectric layers and connections between the metal layers are provided by xe2x80x9cvia plugsxe2x80x9d or xe2x80x9cvia studsxe2x80x9d.
Typically in highly dense, sub micron-size integrated circuit devices, where small features are desired, three, four or more levels of interconnection metallization may be required. Also, it becomes necessary that each level of interconnection be applied to a planar surface, so that CMP (Chemical Mechanical Polishing) becomes a requisite process for fabrication of the multilevel structures.
Therefore, it is imperative that the multiple layers of dielectric materials and conducting materials be compatible in terms of mutual adhesion and chemical stability. Also, the manufacturing processes used for the individual layers, such as deposition processes, pattern formation processes and planarization processes, must be compatible with both previously deposited layers and with subsequently deposited layers and the steps of forming thereof. For example, during manufacturing process heat treatment steps the mutual adhesion between multiple layers must not be degraded and result in delamination of layers.
Also, as circuit density increases the RC (resistance X capacitance) delay becomes increasingly critical. In order to reduce the RC delay the higher conductivity of copper compared to aluminum offers improvement and lower dielectric constant insulators are desirable to replace SiO2 which has a dielectric constant (k) of approximately 4.0. FSG (F doped SiO2), having kxcx9c3.5, is a candidate for a low-k dielectric.
However, when using FSG (F doped SiO2) in composite dielectric layers as shown in FIG. 1, where the FSG (F doped SiO2) layer 10 is passivated by a two-layer passivation layer comprising undoped silicon oxide 11 deposited by HDP (High Density Plasma) deposition and silicon nitride 12 deposited by plasma enhanced deposition onto the undoped silicon oxide 11, delamination of the FSG layer occurs during subsequent manufacturing heat treatment cycles. The cause of this delamination is believed to be due to out-diffusion of F atoms from the FSG layer through the undoped silicon oxide and into the silicon nitride layer. During heat treatment cycles the FSG layer reacts with the silicon nitride layer, delamination bubbles occur, and the FSG layer begins to peel.
Therefore, an important challenge in the fabrication of multilevel dielectric structures involving FSG and silicon nitride layers is to prevent delamination of these layers during and subsequent to their deposition.
Numerous patents address processes of protecting dielectric layers and metal layers from deleterious effects during subsequent processing steps. For example, U.S. Pat. No. 5,830,804 entitled xe2x80x9cEncapsulated Dielectric And Method Of Fabricationxe2x80x9d granted Nov. 3, 1999 to James M. Cleeves shows SRO (Silicon Rich Oxide) used as an encapsulating layer to seal a sensitive dielectric, such as spin-on-glass or polyimide, to prevent their attack and/or outgassing during subsequent processing steps.
U.S. Pat. No. 5,567,635 entitled xe2x80x9cMethod Of Making A Three Dimensional Trench EEPROM Cell Structurexe2x80x9d granted Oct. 22, 1996 to Alexandre Acovic et al. teaches the use of a SRO (Silicon Rich Oxide) layer as a capacitor layer in an EEPROM (Electrically Erasable Programmable Read Only Memory) cell structure.
U.S. Pat. No. 5,858,875 entitled xe2x80x9cIntegrated Circuits With Borderless Viasxe2x80x9d granted Jan. 12, 1999 to Henry Wei-Ming Chung et al. describes a method of forming metal lines using etch stop layers.
U.S. Pat. No. 5,756,396 entitled xe2x80x9cMethod Of Making A Multi-Layer Wiring Structure Having Conductive Sidewall Etch Stoppers And A Stacked Plug Interconnectxe2x80x9d granted May 26, 1998 to Chung-Kuang Lee et al. describes a method of electrically connecting two wiring layers in which conductive sidewall spacers composed of titanium nitride and tungsten are formed on a first layer metal wiring pattern. The sidewall spacers act as an etch stop for a via etch to contact the first layer metal wiring pattern and also increase the contact area of the wiring layers. A tungsten plug with an outer Tin barrier layer is formed filling the via contacting the first layer metal wiring pattern and then a second layer metal wiring pattern is formed also having TiN and tungsten sidewall spacers. The second layer sidewall spacers, also, fill in the TiN plug barrier layer.
The present invention is directed to a novel composite dielectric structure and method of forming thereof which prevents delamination of FSG (F-doped SiO2) and allows FSG to be used in combination with plasma deposited silicon nitride without deleterious peeling or delamination during heat treatment cycles applied subsequently to the formation of the FSG and silicon nitride dielectric layers.
It is a general object of the present invention to provide an improved composite dielectric structure and method of forming thereof which prevents delamination of FSG (F-doped SiO2) and allows FSG to be used in combination with plasma deposited silicon nitride without deleterious peeling or delamination during heat treatment cycles applied subsequently to the formation of the FSG and silicon nitride dielectric layers.
A more specific object of the present invention is to provide an improved composite dielectric structure and method of forming thereof which prevents delamination of FSG (F-doped SiO2) and allows FSG to be used as the interlevel dielectric between successive conducting interconnection patterns in multilevel integrated circuit structures.
In accordance with the present invention, the above and other objectives are realized by using a method of fabricating a multiple layer interlevel dielectric composite on a semiconductor substrate comprising the steps of: providing a semiconductor substrate; forming a first dielectric layer, comprising FSG (F doped SiO2), onto said semiconductor substrate; forming a second dielectric layer, comprising undoped silicon oxide deposited by HDP (High Density Plasma) deposition, onto said first dielectric layer; forming a third dielectric layer, comprising silicon-rich silicon oxide deposited by HDP (High Density Plasma) deposition, onto said second dielectric layer; and forming a fourth dielectric layer, comprising silicon nitride deposited by plasma enhanced deposition, onto said third dielectric layer.
In a second embodiment of the present invention, the above and other objectives are realized by using a method of fabricating a multiple layer interlevel dielectric composite on a semiconductor substrate comprising the steps of: providing a semiconductor substrate; forming a first dielectric layer, comprising FSG (F doped SiO2), onto said semiconductor substrate; forming a second dielectric layer, comprising silicon-rich silicon oxide deposited by HDP (High Density Plasma) deposition, onto said first dielectric layer; and forming a third dielectric layer, comprising silicon nitride deposited by plasma enhanced deposition, onto said second dielectric layer.
In a third embodiment of the present invention, the above and other objectives are realized by an improved multiple layer interlevel dielectric composite structure for use between successive layers of conducting interconnection patterns on a semiconductor substrate, formed from a first dielectric layer comprising FSG (F doped SiO2) deposited onto said semiconductor substrate, a second dielectric layer comprising undoped silicon oxide deposited by HDP (High. Density Plasma) deposition onto said first dielectric layer, a third dielectric layer comprising silicon-rich silicon oxide deposited by HDP (High Density Plasma) deposition onto said second dielectric layer, and a fourth dielectric layer comprising silicon nitride deposited by plasma enhanced deposition onto said third dielectric layer.
And in yet a fourth embodiment of the present invention, the above and other objectives are realized by an improved multiple layer interlevel dielectric composite structure for use between successive layers of conducting interconnection patterns on a semiconductor substrate, formed from a first dielectric layer comprising FSG (F doped SiO2) deposited onto said semiconductor substrate, a second dielectric layer comprising silicon-rich silicon oxide deposited by HDP (High Density Plasma) deposition onto said first dielectric layer, and a third dielectric layer comprising silicon nitride deposited by plasma enhanced deposition onto said second dielectric layer.